Viewing posts from March, 2012

8: The *actual* $a instructions, pt. 2

Time to think about the data store a bit. The d0/d2/d4/d6 opcodes are very likely just ld/st instructions targetting it. However, the channel switch sequence is supposed to read/write the context DMA object, and the VP architecture diagram shows a line connecting the data store to the memory interface. This means we should likely be looking for a way to launch a bulk transfer between the data store and the VM. Obviously, this should be done by the unknown instructions at the start and end of the channel switch sequences.

7: the *actual* $a instructions, pt. 1

Today I'll attempt to look at the channel switch microcode. Its only tasks should be loading/storing the context data and some administrative stuff.